Supporter: EU FP7
Partners: Technical University of Denmark (Denmark), AbsInt Angewandte Informatik (Germany), GMV (Portugal), Intecs (Italy), University of York (United Kingdom), Technical University of Eindhoven (Netherlands), Vienna University of Technology (Austria), The Open Group (United Kingdom)
Started: 1. September 2011
Finished: 31. August 2014
Contact Person: Peter Puschner
Team: Peter Puschner, Daniel Prokesch, Bekim Chilku, Benedikt Huber, Jens Knoop (Complang), Stefan Hepp (Complang)

Standard computer architecture is driven by the following paradigm: Make the common case fast and the uncommon case correct.
This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modeling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative. We need a sea change and we shall take the constructive approach by designing computer architectures where predictable timing is a first-order design factor. For real-time systems we propose to design architectures with a new paradigm: Make the worst case fast and the whole system easy to analyze. Despite the advantages of analyzable system resources, only a few research projects exist in the field of hardware optimized for the WCET. Within the project we propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc.) are a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) provide a solution for the need of more processing power in the real-time domain. Next to the hardware (processor, interconnect, memories), a compiler infrastructure is developed in the project. WCET aware optimization methods are developed along with detailed timing models such that the compiler benefits from the known behavior of the hardware. The WCET analysis tool aiT is adapted to support the developed hardware and guide the compilation.

Detailed project information is provided on the official project website http://www.t-crest.org/