Raimund Kirner

Since March 2010 I am with the Compiler Technology and Computer Architecture Group at the University of Hertfordshire. Please have a look at my homepage at the CTCA group for updated information on my research activities.


Adjunct Professor (Habilitation)


Raimund Kirner
Affiliated Staff Privatdoz. Dipl.-Ing. Dr.techn.
Phone +43(1)58801-18211
Fax +43(1)58801-18299

Vienna University of Technology
Institute of Computer Engineering
Cyber-Physical Systems
DE0319 Treitlstraße 3 1040 Wien Österreich


Raimund Kirner is an Adjunct Professor (Habilitation) at the Institut für Technische InformatikReal-Time Systems Group at the Vienna University of Technology. He has studied Computer Science at TU Vienna and received the Dipl.-Ing. (Master's) degree in 2000. He received the Dr.techn. (PhD) degree

from TU Vienna in 2003.


Info: If you are interested in a Master's Thesis done in collaboration of TU Vienna and University of Hertfordshire (close to London), including a stay in England, you may contact me.  We also offer internships, enabling a short stay in England.



The research interests of Raimund Kirner include the following topics:

Parallel Computing
Parallel computing offers the challenge that the individual jobs executing in parallel may influence each other, for example, with regards of extra-functional properties like execution time. Adequate hardware and software architectures are necessary to bridge the gap between the many-core computing and embedded computing. Further, many-core computing also offers to be the base for novel approaches of robust computing.
In collaboration with Alex Shafarenko I am the local coordinator at UH of the FP7 project ADVANCE, where the goal is to use of probabilistic runtime information to optimize S-Net programs. This includes program transformations and resource management like load balancing.  Since 2012 I am the principal investigator at UH of the ARTMIS project CRAFTERS, where the goal is to develop multi-core systems, including predictability and reliability.
Worst-Case Execution Time Analysis
The worst-case execution time (WCET) of a program is the maximum execution time it can take on a concrete target hardware. The knowledge of the WCET of tasks is crucial for the design of real-time systems. Only if safe upper bounds for the WCET of all time-critical tasks have been established, it becomes possible to verify the timeliness of the whole real-time system.
Raimund Kirner is the principal investigator of the FORTAS-rt project, funded by the FWF. In cooperation with the research group of Prof. Helmut Veith, the reseach of FORTAS-rt focues on measurement-based timing analysis using efficient automatic generation of test-data.
Compiler Support for WCET Analysis
Due to complexity limits and only partially available system descriptions during the analysis, the calculation of the WCET requires the provision of additional control flow information (flow facts). For convenience of the developers the flow facts have to be provided at source-code level. But the WCET analysis has to be performed at object-code level to obtain tight results. Therefore, it is necessary by the compiler to transform the flow facts from source-code to object-code level. The flow facts have to be transformed in case of control-flow changing code optimizations performed by the compiler.
Raimund Kirner is the principal investigator of the CoSTA project, funded by the FWF. The research in CoSTA focuses on the generation of predictable code patterns on processors with timing anomalies and on the transformation of flow facts from source code to object code.
Predictable Computer Architectures
WCET analysis is quite complex on modern computer systems. Modern processors that contains features like pipelines or caches maintain an internal state to improve peak performance. Modelling this internal state exactly to calculate a tight WCET value is often infeasible. The infeasibility comes from the state explosion due to input-data-dependent control flow and cache states. The development of more predictable software and hardware concepts will reduce the complexity of WCET analysis. Specific programming paradigms can help to reduce the complexity of control-flow path analysis.
Verification of Embedded Systems
Systematic testing is becoming increasingly important in the development of embedded systems. Within our research we focus on techniques to automate the generation of test cases using formal techniques like model checking.
Raimund Kirner has worked together with Peter Puschner as local coordinator of the TeDES project at the TU-Vienna. Within TeDES, a functional testing framework with automatic test case generation has been developed.

Presentations available online:

Raimund Kirner is a member of the IEEE Computer Society, the ACM, and the Austrian Computer Society (OCG).


Publications and research reports are described in the publication page.


Information about the currently supervised courses can be found at TUWIS.


Selected contributions of students to the courses "Ausgewählte Kapitel der Technischen Informatik" are collected in an online journal.