• AMADEOS: Architecture for Multi-criticality Agile Dependable Evolutionary Open System-of-Systems
  2013 – 2016 / European Commission

2025

• Kopetz, H. (2025). A short Note on Data versus Information.
  DOI: 10.34726/11279 / Download: PDF

2019

• Kopetz, H. (Ed.). (2019). Simplicity is Complex : Foundations of Cyber-Physical System Design. Springer.
  DOI: 10.1007/978-3-030-20411-2

2016

• Frömel, B., Kopetz, H. (2016). Interfaces in Evolving Cyber-Physical Systems-of-Systems. In Cyber-Physical Systems of Systems (pp. 40–72). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-47590-5_2
• Kopetz, H., Bondavalli, A., Brancati, F., Frömel, B., Höftberger, O., Iacob, S. (2016). Emergence in Cyber-Physical Systems-of-Systems (CPSoSs). In Cyber-Physical Systems of Systems (pp. 73–96). Springer International Publishing. Peer-reviewed.
  DOI: 10.1007/978-3-319-47590-5_3
• Ceccarelli, A., Bondavalli, A., Froemel, B., Hoeftberger, O., Kopetz, H. (2016). Basic Concepts on Systems of Systems. In Cyber-Physical Systems of Systems (pp. 1–39). Springer International Publishing.
  DOI: 10.1007/978-3-319-47590-5_1
• Bondavalli, A., Bouchenak, S., Kopetz, H. (Eds.). (2016). Cyber-Physical Systems of Systems. Foundations – A Conceptual Model and Some Derivations: The AMADEOS Legacy. Springer International Publishing.
  DOI: 10.1007/978-3-319-47590-5

2015

• Kopetz, H., Frömel, B., Höftberger, O. (2015). Direct versus stigmergic information flow in systems-of-systems. In 2015 10th System of Systems Engineering Conference (SoSE). 10th Annual Systems of Systems Engineering Conference 2015, San Antonio, United States of America (the). Peer-reviewed.
  DOI: 10.1109/sysose.2015.7151963
• Kopetz, H. (2015). Simplification Principles in the Design of Cyber-Physical System-of-Systems. In Complex Systems Design & Management (pp. 39–51). Springer International Publishing.
  DOI: 10.1007/978-3-319-26109-6_3
• Kopetz, H., Höftberger, O., Frömel, B., Brancati, F., Bondavalli, A. (2015). Towards an understanding of emergence in systems-of-systems. In 2015 10th System of Systems Engineering Conference (SoSE). 10th Annual Systems of Systems Engineering Conference 2015, San Antonio, United States of America (the). Peer-reviewed.
  DOI: 10.1109/sysose.2015.7151925

2014

• Kopetz, H. (2014). A Conceptual Model for the Information Transfer in System of Systems. In Proc. of the 17th IEEE International Symposium on Object/Component-Oriented Real-Time Distributed Computing (pp. 17–24). Peer-reviewed.
  HDL: 20.500.12708/55746
• Steiner, W., Bonomi, F., Kopetz, H. (2014). Towards synchronous deterministic channels for the Internet of Things. In Proc. of the IEEE World Forum on Internet of Things 2014 (WF-IoT2014) (pp. 433–436). IEEE.
  HDL: 20.500.12708/55750
• Kopetz, H. (2014). Keynote: From embedded systems to systems of systems. In 2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (pp. 292–292). IEEE. Invited.
  DOI: 10.1109/isorc.2014.58

2011

• Wasicek, A., El Salloum, C., Kopetz, H. (2011). Authentication in Time-Triggered Systems using Time-delayed Release of Keys. In 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC) (pp. 31–39). IEEE. Peer-reviewed.
  HDL: 20.500.12708/53909
• Mikolasek, V., Kopetz, H. (2011). Roll-Forward Recovery with State Estimation. In 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC) (pp. 179–186). IEEE. Peer-reviewed.
  HDL: 20.500.12708/53910

2010

• Wasicek, A., Kopetz, H., El Salloum, C. (2010). A System-on-a-Chip Platform for Mixed-Criticality Applications. In 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing. Proceedings of 13th IEEE International Symposium on Object/component/service-oriented Real-time distributed computing (ISORC’10), Carmona, Spain. IEEE. Peer-reviewed.
  DOI: 10.1109/isorc.2010.43

2009

• Obermaisser, R., El Salloum, C., Huber, B., Kopetz, H. (2009). From a Federated to an Integrated Automotive Architecture. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (pp. 956–965). IEEE. Peer-reviewed.
  DOI: 10.1109/tcad.2009.2014005
• Obermaisser, R., Kopetz, H., Kuster, S. (2009). GENESYS (GENeric Embedded SYStem) - A Candidate for an ARTEMIS Cross-Domain Reference Architecture for Embedded Systems. ARTEMIS Magazine, 5, 32–34.
  HDL: 20.500.12708/166246
• Obermaisser, R., Salloum, C. E., Huber, B., Kopetz, H. (2009). Fundamental Design Principles for Embedded Systems: The Architectural Style of the Cross-Domain Architecture GENESYS. In 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing. IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Newport Beach, United States of America (the). IEEE. Peer-reviewed.
  DOI: 10.1109/isorc.2009.12

2008

• Salloum, C. E., Obermaisser, R., Huber, B., Kopetz, H. (2008). A Novel Naming Scheme for System-on-a-Chips Supporting Dynamic Resource Management. In 2008 Seventh European Dependable Computing Conference. Seventh European Dependable Computing Conference (EDCC-7), Kaunas, Lithuania, EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/edcc-7.2008.21
• Obermaisser, R., Salloum, C. E., Huber, B., Kopetz, H. (2008). The time-triggered System-on-a-Chip architecture. In 2008 IEEE International Symposium on Industrial Electronics. IEEE International Symposium on Industrial Electronics, 2008. ISIE 2008, Cambridge, UK, EU. Peer-reviewed.
  DOI: 10.1109/isie.2008.4677135
• Kopetz, H. (2008). Composability in the time-triggered system-on-chip architecture. In Proceedings of the 21st Annual IEEE International SoC Conference (pp. 87–90). Peer-reviewed.
  HDL: 20.500.12708/52648
• Kopetz, H. (2008). The Complexity Challenge in Embedded System Design. In 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC). The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/isorc.2008.14
• Kopetz, H. (2008). Wrong Assumptions and Neglected Areas in Embedded Systems Research. In 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC). The 11th IEEE Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Orlando, Florida, USA, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/isorc.2008.15
• Paukovits, C., Kopetz, H. (2008). Concepts of Switching in the Time-Triggered Network-on-Chip. In 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2008), Kaohsiung, Taiwan, Non-EU. IEEE Computer Society. Peer-reviewed.
  DOI: 10.1109/rtcsa.2008.18

2007

• Ademaj, A., Hanzlik, A., Kopetz, H. (2007). Tolerating Arbitrary Failures in a Master-Slave Clock-Rate Correction Mechanism for Time-Triggered Fault-Tolerant Distributed Systems with Atomic Broadcast. In Proceedings of the 15th International Conference on Real-Time and Network Systems (RTNS’07) (pp. 215–224). Institut National Polytechnique de Lorraine. Peer-reviewed.
  HDL: 20.500.12708/51845
• Kopetz, H. (2007). Why do we need a Sparse Global Time-Base in Dependable Real-time Systems? In ISPCS Proceedings (p. 5). Peer-reviewed.
  HDL: 20.500.12708/51882
• Ademaj, A., Kopetz, H. (2007). Time-Triggered Ethernet and IEEE 1588 Clock Synchronization. In ISPCS 2007 Proceedings (p. 3). Peer-reviewed.
  HDL: 20.500.12708/51883
• El Salloum, C., Obermaisser, R., Huber, B., Paulitsch, H., Kopetz, H. (2007). A time-triggered system-on-a-chip architecture with integrated support for diagnosis. In Workshop Digest, Diagnostic Services in Network-on-Chips (p. 2). DATE’07. Peer-reviewed.
  HDL: 20.500.12708/51901
• Paulitsch, H., Obermaisser, R., El Salloum, C., Huber, B., Kopetz, H. (2007). A Diagnostic Unit for the time-triggered System-on-a-Chip architecture. In Workshop Digest, Diagnostic Services in Network-on-Chips (p. 2). DATE’07. Peer-reviewed.
  HDL: 20.500.12708/51902
• Kopetz, H. (2007). Modeling of Software-Hardware Complexes. In IFIP – The International Federation for Information Processing (pp. 431–432). Springer Boston. Peer-reviewed.
  DOI: 10.1007/978-0-387-72258-0_39
• Obermaisser, R., Kopetz, H., El Salloum, C., Huber, B. (2007). Error Containment in the Time-Triggered System-On-a-Chip Architecture. In IFIP – The International Federation for Information Processing (pp. 339–352). Springer Boston. Peer-reviewed.
  DOI: 10.1007/978-0-387-72258-0_29
• Kopetz, H., Obermaisser, R., El Salloum, C., Huber, B. (2007). Automotive Software Development for a Multi-Core System-on-a-Chip. In Fourth International Workshop on Software Engineering for Automotive Systems (SEAS ’07), Proceedings. SEAS’07, Minneapolis, USA, Non-EU. IEEE. Peer-reviewed.
  DOI: 10.1109/SEAS.2007.2
• Kopetz, H. (2007). Zuverlässige Elektronik-Systeme im Verkehrswesen. In Informatik bewegt - Informationstechnik in Verkehr und Logistik (pp. 55–79). acatech.
  HDL: 20.500.12708/52112

2006

• Kopetz, H., Ademaj, A., Hanzlik, A. (2006). Combination of clock-state and clock-rate correction in fault-tolerant distributed systems. Real-Time Systems, 33, 139–173. Peer-reviewed.
  HDL: 20.500.12708/173417
• Kopetz, H. (2006). Pulsed Data Streams. In B. Kleinjohann, L. Kleinjohann, R. J. Machado, C. Pereira, P. S. Thiagarajan (Eds.), 5th IFIP Working Conference on Distributed and Parallel Embedded Systems, Proceedings (pp. 105–114). Springer. Peer-reviewed.
  HDL: 20.500.12708/51770
• Rumpler, B., Kopetz, H. (2006). Design Comprehension of Time-Triggered Real-Time Systems. In Proceedings of the Junior Scientist Conference 2006 (JSC’06) (pp. 63–64). Peer-reviewed.
  HDL: 20.500.12708/51492
• Steinhammer, K., Kopetz, H. (2006). Time-Triggered Ethernet. In Junior Scientist Conference - JSC 2006 (pp. 73–74). Peer-reviewed.
  HDL: 20.500.12708/51598
• Grillinger, P., Ademaj, A., Steinhammer, K., Kopetz, H. (2006). Software Implementation of Time-Triggered Ethernet Controller. In Workshop on Factory Communication Systems - WFCS 2006, Proceedings (pp. 145–150). Peer-reviewed.
  HDL: 20.500.12708/51599
• Steinhammer, K., Grillinger, P., Ademaj, A., Kopetz, H. (2006). A Time-Triggered Ethernet (TTE) Switch. In Proceedings of the Design, Automation and Test in Europe (p. 6). Peer-reviewed.
  HDL: 20.500.12708/51356
• Steiner, W., Kopetz, H. (2006). The Startup Problem in Fault-Tolerant Time-Triggered Communication. In International Conference on Dependable Systems and Networks 2006, Proceedings of the (pp. 35–44). Peer-reviewed.
  HDL: 20.500.12708/51430
• Ademaj, A., Steinhammer, K., Grillinger, P., Kopetz, H., Hanzlik, A. (2006). Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology. In 19th International Conference on Architecture of Computing systems (ARCS’06), Proceedings of the. 19th International Conference on Architecture of Computing systems (ARCS), Frankfurt/Main, Germany, EU. Springer-Verlag. Peer-reviewed.
  HDL: 20.500.12708/51432
• El Salloum, C., Obermaisser, R., Huber, B., Kopetz, H., Suri, N. (2006). Supporting Heterogeneous Applications in the DECOS Integrated Architecture. In International DECOS Workshop. International DECOS Workshop, Vienna, Austria, Austria. Peer-reviewed.
  HDL: 20.500.12708/51440

2005

• Kopetz, H., Obermaisser, R., Schmid, U. (2005). Dependable Embedded Systems Research at TU Vienna. Elektrotechnik Und Informationstechnik : E i, 122(1), 33–37. Invited and peer-reviewed.
  DOI: 10.1007/BF03054020
• Kopetz, H., Bauer, G. (2005). Time Triggered Communication Networks. In Industrial Information Technology Handbook. CRC Press. Peer-reviewed.
  HDL: 20.500.12708/25345
• Kopetz, H., Bauer, G., Steiner, W. (2005). Dependable Time-Triggered Communication. In The Industrial Communication Technology Handbook. CRC Press. Peer-reviewed.
  HDL: 20.500.12708/25348
• Schmid, U., Kopetz, H., Puschner, P., Mayerhofer, L., Steininger, A., Grünbacher, H., Kastner, W., Krall, A. (2005). Antrag UNI-Infrastruktur III, Embedded Systems Research Cluster.
  HDL: 20.500.12708/33035
• Obermaisser, R., Henrich, E., Kim, K., Kopetz, H., Kim, M. H. (2005). Integration of two Complementary Time-Triggered Technologies: TMO and TTP. In Proceedings of the International Embedded Systems Symposium 2005 (pp. 1–12). Springer.
  HDL: 20.500.12708/51079
• Obermaisser, R., Peti, P., Kopetz, H. (2005). Virtual Networks in an Integrated Time-Triggered Architecture. In Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems, 2005. IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS), Sedona, Arizona, Austria. Peer-reviewed.
  HDL: 20.500.12708/51080
• Kim, K., Recker, W., Tsai, W. T., Kopetz, H., Puschner, P. (2005). DECOS-TADE Collaboration. In IST-NSF Workshop on Transatlantic Research Agenda on Future Challenges in Embedded Systems Design (p. 7). Information Society Technologies/National Science Foundation. Peer-reviewed.
  HDL: 20.500.12708/51114
• Kopetz, H. (2005). TTA Supported Service Availability. In M. Malek, E. Nett, N. Suri (Eds.), Service Availability - Second International Availability Symposium (pp. 1–14). Springer.
  HDL: 20.500.12708/51769
• Peti, P., Obermaisser, R., Kopetz, H. (2005). Out-of-Norm Assertions. In Proceedings of the elventh IEEE Real-Time and Embedded Technology and Applications Symposium (pp. 280–291). IEEE Computer Society. Peer-reviewed.
  HDL: 20.500.12708/50998
• Obermaisser, R., Peti, P., Kopetz, H. (2005). Virtual Gateways in the DECOS Integrated Architecture. In Proceedings of the 13th Workshop on Parallel and Distributed Real-Time Systems 2005 (WPDRTS). Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), Orlando, Florida, USA, Austria. Peer-reviewed.
  HDL: 20.500.12708/50999
• Peti, P., Obermaisser, R., Ademaj, A., Kopetz, H. (2005). A Maintenance-Oriented Fault Model for the DECOS Integrated Diagnostic Architecture. In Proceedings of the 13th Workshop on Parallel and Distributed Real-Time Systems 2005 (WPDRTS) Author(s). Workshop on Parallel and Distributed Real-Time Systems (WPDRTS), Orlando, Florida, USA, Austria. Peer-reviewed.
  HDL: 20.500.12708/51000
• Kopetz, H., Ademaj, A., Grillinger, P., Steinhammer, K. (2005). The Time-Triggered Ethernet (TTE) Design. In Proceedings of the 8th IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC) (pp. 22–33). IEEE Computer Society. Peer-reviewed.
  HDL: 20.500.12708/51016

2004

• Kopetz, H., Bauer, G., Obermaisser, R., Peti, P., Puschner, P. (2004). The Time-Triggered Architecture: Short Summary of Recent Work and Future Trends.
  HDL: 20.500.12708/32970
• Kopetz, H. (2004). On the Fault Hypothesis for a Safety-Critical Real-Time System. In H. Kopetz (Ed.), On the Fault Hypothesis for a Safety-Critical Real-Time System.
  HDL: 20.500.12708/51359
• Kopetz, H. (2004). On the Fault Hypothesis for a Safety-Critical Real-Time System. In H. Kopetz (Ed.), On the Fault Hypothesis for a Safety-Critical Real-Time System.
  HDL: 20.500.12708/51359

2002

• Elmenreich, W., Haidinger, W., Kopetz, H., Losert, T., Obermaisser, R., Paulitsch, M., Trödhandl, C. (2002). Initial Demonstration of Smart Sensor Case Study.
  HDL: 20.500.12708/32826
• Kopetz, H. (2002). On the Specification of Linking Interfaces in Distributed Real-Time Systems.
  HDL: 20.500.12708/32827
• Kopetz, H. (2002). Time-Triggered Real-Time Computing.
  HDL: 20.500.12708/32835
• Kopetz, H., Obermaisser, R. (2002). Temporal composability.
  HDL: 20.500.12708/32843
• Bauer, G., Kopetz, H., Steiner, W. (2002). Byzantine Fault Containment in TTP/C.
  HDL: 20.500.12708/32844
• Aslam-Mir, S., Haidinger, W., Elmenreich, W., Losert, T., Kopetz, H. (2002). Smart Transducers Interface Specification.
  HDL: 20.500.12708/32857

2001

• Kopetz, H., Bauer, G., Poledna, S. (2001). Tolerating Arbitrary Node Failures in the Time-Triggered Architecture. In Proceedings of the SAE 2001 World Congress. SAE World Congress, Detroit, MI, USA, Austria.
  HDL: 20.500.12708/50884
• Bauer, G., Kopetz, H., Puschner, P. (2001). Assumption Coverage under Different Failure Modes in the Time-Triggered Architecture. In Proceedings of the 8th IEEE International Conference on Emerging Technologies and Factory Automation (pp. 333–341).
  HDL: 20.500.12708/50882
• Elmenreich, W., Haidinger, W., Kopetz, H. (2001). Interface Design for Smart Transducers. In Proceedings of the IEEE Instrumentation and Measurement Technology Conference (IMTC) (pp. 1642–1647).
  HDL: 20.500.12708/50880
• Kopetz, H. (2001). The Three Interfaces of a Smart Transducer. In Proceedings of the FeT`2001 - 4th IFAC International Conference on Fieldbus Systems and their Applications. IFAC International Conference on Fieldbus Systems and their Applications, Nancy, France, Austria. Peer-reviewed.
  HDL: 20.500.12708/50877
• Kopetz, H. (2001). A Universal Smart Transducer Interface. In Proceedings of the V Simpósio Brasileiro de Automação Inteligente (pp. 1–8). Peer-reviewed.
  HDL: 20.500.12708/50876
• Kopetz, H. (2001). The Temporal Specification of Interfaces in Distributed Real-Time Systems. In Proceedings of the EMSOFT (pp. 223–236). Peer-reviewed.
  HDL: 20.500.12708/50869
• Kopetz, H., Holzmann, M., Elmenreich, W. (2001). A Universal Smart Transducer Interface: TTP/A. Computer Systems Science and Engineering, 16(2), 71–77. Peer-reviewed.
  HDL: 20.500.12708/174788

2000

• Kopetz, H., Holzmann, M., Elmenreich, W. (2000). A Universal Smart Transducer Interface: TTP/A. In Proceedings of the third IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC 2000). IEEE International Symposium on Object-oriented Real-time distributed Computing (ISORC), Newport Beach, CA, USA, Austria. Peer-reviewed.
  HDL: 20.500.12708/50867
• Kopetz, H., Elmenreich, W., Mack, C. (2000). A Comparison of LIN and TTP/A. In Proceedings of the 3rd IEEE International Workshop on Factory Communication Systems (WFCS 2000) (pp. 99–107). Peer-reviewed.
  HDL: 20.500.12708/50894
• Bauer, G., Frenning, T., Jonsson, A.-K., Kopetz, H., Temple, C. (2000). A Centralized Approach for Avoiding the Babbling-Idiot Failure in the time-Triggered Architecture. In Proceedings of the ICDSN 2000. ICDSN, New York, USA, Austria.
  HDL: 20.500.12708/50895
• Kopetz, H. (2000). Software Engineering for Real-Time: A Roadmap. In Proceedings of the 22nd International conference on Future of Software Engineering (FoSE). International Conference on Future of Software Engineering, Limerick, Ireland, Austria. Peer-reviewed.
  HDL: 20.500.12708/50896
• Bauer, G., Kopetz, H. (2000). Transparent Redundancy in the Time-Triggered Architecture. In Proceedings of the International Conference on Communications in Computing. International Conference on Communications in Computing, Las Vegas, USA, Austria.
  HDL: 20.500.12708/50898
• Kopetz, H. (2000). Composability in the Time-Triggered Architecture. In Proceedings of the SAE International Congress and Exhibition (2000-01-1382). SAE International Congress and Exhibition, Detroit, USA, Austria.
  HDL: 20.500.12708/50899

• Kopetz, H. (2015). From Embedded Systems to System of Systems. ITASC Workshop: Intelligent Transportation and Smart City, Shanghai, China. Invited.
  HDL: 20.500.12708/86183
• Kopetz, H. (2014). Systems of Systems Need a Global Time. 23rd NIST-ATIS Synchronization Workshop, San Jose, United States of America (the). Invited.
  HDL: 20.500.12708/85918
• Kopetz, H. (2014). Why a Global Time is Needed in a Dependable SoS. Engineering Dependable Systems of Systems (EDSoS) 2014, Newcastle, United Kingdom of Great Britain and Northern Ireland (the). Invited.
  HDL: 20.500.12708/85920
• Kopetz, H. (2014). From Embedded Systems to Systems of Systems. 27th International Conference on VLSI Design 2014, Mumbai, India. Invited.
  HDL: 20.500.12708/85921
• Paulitsch, H., Paukovits, C., El Salloum, C., Kopetz, H. (2009). Fault Isolation with Intermediate Checks of End-to-end Checksums in the Time-Triggered System-on-Chip Architecture. DSNOC’09 (DATE Friday Workshop), Nice, France.
  HDL: 20.500.12708/84901

2015

• Höftberger, O. (2015). Knowledge-based dynamic reconfiguration for embedded real-time systems [Dissertation, Technische Universität Wien]. reposiTUm.
  DOI: 10.34726/hss.2015.31540 / Download: PDF

2011

• Wasicek, A. R. (2011). Security in Time-Triggered Systems [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/161503
• Perez Cerrolaza, J. M. (2011). Executable time-triggered model (E-TTM) for the development of safety-critical embedded systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-44622
  HDL: 20.500.12708/11307 / Download: PDF
• Mair, T. (2011). Validation middleware for mixed criticality networks [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-45471
  HDL: 20.500.12708/11261 / Download: PDF
• Suethanuwong, E. (2011). Performance evaluation and optimization of standard-ethernet traffic in TTEthernet systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-60071
  HDL: 20.500.12708/10103 / Download: PDF

2008

• Kraut, H. (2008). Reliability assessment of DECOS System-on-a-Chip components [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-22923
  HDL: 20.500.12708/11025 / Download: PDF
• Paukovits, C. P. (2008). The time-triggered system-on-chip architecture [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-22787
  HDL: 20.500.12708/13436 / Download: PDF
• Strnad, T. (2008). Validation of the DECOS encapsulated execution environment [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-28387
  HDL: 20.500.12708/13429 / Download: PDF
• Huber, B. (2008). Resource management in an integrated time-triggered architecture [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-15983
  HDL: 20.500.12708/14020 / Download: PDF
• Rumpler, B. (2008). Design comprehension of embedded real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-26639
  HDL: 20.500.12708/10812 / Download: PDF
• Weirich, B. (2008). A resource management scheme for the TT-SoC architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-28745
  HDL: 20.500.12708/11908 / Download: PDF

2007

• Schrei, A. (2007). Secure internet interfaces for an integrated time-triggered architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19689
  HDL: 20.500.12708/14359 / Download: PDF
• El-Salloum, C. (2007). Interface design in the time-triggered system-on-chip architecture [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18578
  HDL: 20.500.12708/14362 / Download: PDF
• Seiger, R. (2007). An extensible interface subsystem for a novel time-triggered system-on-a-chip architecture [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-18929
  HDL: 20.500.12708/14239 / Download: PDF
• Schlager, M. (2007). Interface design for hardware-in-the-loop simulation of real-time systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-17824
  HDL: 20.500.12708/14216 / Download: PDF
• Pucher, C. (2007). A framework for validation of virtual gateways in the DECOS architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-22245
  HDL: 20.500.12708/11070 / Download: PDF
• Schüller, F. (2007). Diagnosis of CAN-based legacy applications in the time-triggered architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-19980
  HDL: 20.500.12708/12491 / Download: PDF
• Engleder, G. A. (2007). Time-triggered network-on-a-chip [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/184146
• Hofer, B. (2007). Experimental evaluation of temporal and spatial partitioning for gateways in integrated architectures [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181913

2006

• Paukovits, C. (2006). Applying model-integrated computing on time-triggered application development [Master Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-37276
  HDL: 20.500.12708/12416 / Download: PDF
• Brandstetter, A. (2006). Scheduling for the Time-Triggered Ethernet [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181326
• Steinhammer, K. (2006). Design of an FPGA-based time-triggered Ethernet system [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181350
• Schörgendorfer, A. (2006). Extended confidence-weighted averaging in sensor fusion [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179560
• Höller, M. (2006). Gateway generation for virtual networks in the DECOS integrated architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185041
• Leiner, B. M. J. (2006). A partitioning operating system based on RTAI-LXRT Linux [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/178061

2005

• Peti, P. (2005). Diagnosis and maintenance in an integrated time-triggered architecture [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-17847
  HDL: 20.500.12708/12759 / Download: PDF
• Losert, T. (2005). Extending CORBA for hard real-time systems [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/177709
• Paulitsch, H. (2005). Fault injection for diagnosis and maintenance in the time-triggered architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179892
• Riezler, D. (2005). Integrating CAN-based legacy applications in the TTA [Master Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179992

2004

• Steiner, W. (2004). Startup and recovery of fault-tolerant time-triggered communication [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/184535
• Benesch, R. (2004). TCP für die time-triggered architecture [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/179288
• Huber, B. (2004). Wireless real-time communication for smart transducer networks [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/177967
• Hanzlik, A. (2004). Investigation of fault-tolerant multi-cluster clock synchronization strategies by means of simulation [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-9301
  HDL: 20.500.12708/14344 / Download: PDF

2003

• Borovicka, M. C. A. V. (2003). Design of a gateway for the interconnection of real-time communication hierarchies [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/181518
• Obermaisser, R. (2003). An integrated architecture for event-triggered and time-triggered control paradigms [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/182872
• Ademaj, A. (2003). Assessment of error detection mechanisms of the time-triggered architecture using fault injection [Dissertation, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/183025

2002

• Paulitsch, M. (2002). Fault-tolerant clock synchronization for embedded distributed multi-cluster systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-13587
  HDL: 20.500.12708/13540 / Download: PDF
• Elmenreich, W. (2002). Sensor fusion in time-triggered systems [Dissertation, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-11148
  HDL: 20.500.12708/13548 / Download: PDF
• Trödhandl, C. (2002). Architectural requirements for TTP/A nodes [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/186248
• Schwarz, M. (2002). Implementation of a TTP/C cluster based on commercial gigabit ethernet components [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/178841
• Eder, C. (2002). Designing a high-performant real-time architecture based on COTS-components [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185223
• Pitzek, S. (2002). Description mechanisms supporting the configuration and management of TTP/A fieldbus systems [Diploma Thesis, Technische Universität Wien]. reposiTUm.
  HDL: 20.500.12708/185227

1993

• Kamali, M. M. (1993). Realisierung eines Network Management Signalling System für das Prototyp einer Weltraumkommunikationseinrichtung (OBIF) [Diploma Thesis, Technische Universität Wien]. reposiTUm. https://resolver.obvsg.at/urn:nbn:at:at-ubtuw:1-12026
  HDL: 20.500.12708/13458 / Download: PDF

• Wilhelm Exner Medaillie
  2005 / Austria
• Vorsitzender d. Wiss. Beirat ACR
  2004 / Austria
• IEEE Technical Achievement Award
  2004
• IGM-Preis
  2001 / Austria
• Mitglied "Rat for Forschung und Technologieentwicklung"
  2000 / Austria
• Wirkliches Mitglied der Österr. Akademie der Wissenschaften
  1998 / Mitgliedschaft / Austria
• Chairman der IFIP WG 10.4
  1996
• Goldenes Verdienstkreuz der Republik Österreich
  1995 / Ehrenkreuz für Wissenschaft und Kunst / Austria
• Fellow of the IEEE
  1993
• Ruf als Direktor an das Max-Plank Institut
  1993 / Germany
• Gründungsmitglied der IFIP 10.4 WG on Dependable Computing
  1980
• Gründungsmitglied der Österr. Computer Gesellschaft
  1975 / Austria

Soon, this page will include additional information such as reference projects, activities as journal reviewer and editor, memberships in councils and committees, and other research activities.

Until then, please visit Hermann’s research profile in TISS.