A Novel Bayesian Network-Based Fault Prognostic Method for Semiconductor Manufacturing Process.*

G. Wang, R.M. Hasani, Y. Zhu, and R. Grosu.

Fault prognostic in various levels of production of semiconductor chips is considered to be a great challenge. To reduce yield loss during the manufacturing process, tool abnormalities should be detected as early as possible during process monitoring. In this paper, we propose a novel fault prognostic method based on Bayesian networks. The network is designed such that it can process both discrete and continuous variables, to represent the correlations between critical deviations and quality control data. Such a network enables us to perform high precision multi-step prognostic on the status of the fabrication process given the current state of the sensory info. Additionally, we introduce a layer-wise approach for efficient learning of the Bayesian-network parameters. We evaluate the accuracy of our prognostic model on a wafer fabrication dataset where our model performs precise next-step fault prognostic by using the control sensory data.

In Proc. of ICIT'17, the 18th International Conference on Industrial Technology, Toronto, Canada, March, 2017.

*This work was partially supported by the Artemis EMC2 Award, the NSF-Frontiers Cyber-Physical Heart Award, FWF-NFN RiSE Award, FWF-DC LMCS Award, FFG Harmonia Award, FFG Em2Apps Award, and the TUW CPPS-DK Award.