Past Projects

Past Research Projects at the Embedded Computing Systems Groups

THETA

THETA

Funding: FWF

Partners: INRIA Rocquencourt, Projet NOVALTIS, France

Time Frame: 08. 12. 2004 - 07. 12. 2009

Contact Persons: Ulrich Schmid

Research Team: Ulrich Schmid

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Accelerator-based Experimental Analysis and Simulation Modeling of Single-Event Transients in VLSI Circuits (EASET)

Funding: FWF stand-alone project

Collaborators: Institute of Electrodynamics, Microwave and Circuit Engineering TU Wien (prof. Zimmermann)

Time Frame: 01. 04. 2014 - 31. 03. 2017

Due to the steadily decreasing feature sizes of modern VLSI circuits, which are in the nanometer range (< 100 nm) nowadays, single-event effects (SEEs) are increasingly dominating the fault rate of VLSI circuits. SEEs occur when junctions of transistors are hit by ionized particles. Such particles primarily originate in high-energy cosmic radiation, affecting a chip either directly (at high altitudes, i.e., in space and aerospace) or indirectly, via interaction with the atmosphere. The primary concern in modern VLSI circuits are transient SEEs: An ionized particle deposits charge along its track, which in turn can cause a single-event transient (SET) signal pulse (0.1-1 ns range). If a sufficiently strong SET propagates to a storage element, it can be latched, thereby producing a single-event upset (SEU).

Robust circuit design, in particular, for critical applications, hence needs models that accurately describe SETs/SEUs and are easy and efficient to use at early design stages. Such models both allow (a) to assess the radiation tolerance of different architectural designs and hardening techniques and (b) to estimate the final error rate of a circuit. The preferred method to accomplish this is simulation-based fault injection at the (analog) electrical level: Typically, a Spice model of the circuit (derived automatically from the design using technology libraries) is augmented with Spice models that simulate SET generation in critical parts of the circuit. The most commonly approach here is single-ended injection of a double-exponential current into the drain of a transistor.

Obviously, the suitability of this method for validating the effectiveness of radiation-hardening measures and predicting soft-error rates stands or falls with the availability of accurate Spice models for SET generation: If it fails to cover important scenarios, one might e.g. overlook situations where radiation-hardening fails. Unfortunately, there is evidence that standard double-exponential Spice models are susceptible to such problems, with respect to several aspects: (1) Inadequate model structure, (2) calibration of model parameters, and (3) SEEs affecting multiple transistors.

Any attempt to developing Spice models that accurately model SET generation (including the above complications) in nanometer VLSI circuits requires a combination of both (a) a detailed understanding of the physical/electrical processes involved and (b) a comprehensive experimental evaluation of SET pulses arising in real circuits. The project EASET is devoted to this purpose: It will use results from accurate analog SET measurements in carefully designed measurement ASICs under micro-beam irradiation to (i) guide the development and (ii) calibrate detailed 3D physical/hybrid TCAD simulation models. The latter is a very powerful means for researching the SET generation process and its parameters in VLSI circuits, and thus also the appropriate basis for developing and validating novel SET generation Spice models for complex nanometer VLSI circuits, which are the primary intended outcome of the project.

The measurement ASICs will include on the one hand the circuits under test, e.g. circuits based on basic combinational and sequential logic and possibly some other topologies like ring oscillators. On the other hand the ASICs will include high speed analog measurement amplifiers which must have minimum influence on the investigated circuit nodes, and they have to include high speed analog 50Ω-output drivers. Additional analog high speed multiplexers are necessary due to the large number of investigated circuit nodes. Consequently, EASET not only addresses interesting fundamental research questions, but also provides results that are relevant in practice. The required competence is ensured by running it as a joint project between the Institut für Technische Informatik and the Institute of Electrodynamics, Microwave and Circuit Engineering at TU Wien, which also includes external collaborations with radiation physics experts e.g. at the GSI in Darmstadt and the PTB in Braunschweig.

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Self-stabilizing Byzantine Fault-Tolerant Distributed Algorithms for Integrated Circuits

Funding: Austrian Science Fund (FWF)

Collaborators: Christoph Lenzen (MPI Saarbrücken), Danny Dolev (Hebrew University), Thomas Nowak (ENS Paris), Michael Hofbauer (TU Wien, Institute of Electrodynamics, Microwave and Circuit Engineering)

Time Frame: 01. 11. 2013 - 31. 10. 2016

Contact Persons: Matthias Függer (Project Head), Ulrich Schmid

Research Team: Matthias Függer (Project Head), Ulrich Schmid, Martin Perner, Robert Najvirt

This project proposes to address robustness issues in very-large scale integrated (VLSI) circuits by means of self-stabilizing Byzantine fault-tolerant distributed algorithms. It aims at the development of the foundations of a suitable framework for correctness proofs and performance analyses for such algorithms, and its application to some representative problems in VLSI circuits. Besides permanent failures due to e.g. manufacturing defects and electrical wear-out, transient faults caused e.g. by ionizing particles, cross-talk and temporarily out-of-spec operating conditions are a major source of concern for the dependability of modern VLSI circuits, in particular, in critical applications domains like aerospace. In sharp contrast to classic fault-tolerance techniques like triple-modular redundancy, self-stabilizing algorithms can recover even from unbounded transient faults, and Byzantine-fault-tolerant self-stabilizing algorithms even allow this to happen in the presence of permanent faults.
VLSI circuits put unique challenges on Byzantine fault-tolerant self-stabilizing distributed algorithms, which have not been addressed by existing solutions at all. Besides the fact that millions of simple gates that continuously compute their outputs based on (past) inputs do not match the classic distributed state machine abstraction employed in distributed algorithms, VLSI circuits provide only very simple basic computation and communication features. As a consequence, neither existing distributed algorithms nor existing modeling and analysis frameworks can be carried over without substantial modification. Nevertheless, the Byzantine fault-tolerant self-stabilizing clock generation approach for VLSI circuits developed recently by the authors (in collaboration with Danny Dolev/Hebrew University and Christoph Lenzen/Weizmann Institute) revealed that it is principally feasible to do so.
The goal of SIC is to develop the foundations of a framework for the rigorous modeling and analysis of Byzantine fault-tolerant self-stabilizing distributed algorithms for VLSI circuits. The work to be performed in SIC involves solving fundamental research questions, in particular, sound and reasonably complete mathematical descriptions of the stabilization process and digital models for metastability generation and propagation, which cannot be solely addressed by engineering solutions in the self-stabilizing context. This work is complemented by devising Byzantine fault-tolerant self-stabilizing solutions for some representative problems in VLSI circuits, like distributed clock generation and reliable broadcast. Using the envisioned modeling and analysis framework, correctness proofs and performance analyses of these algorithms under adequate Byzantine failure models will be provided. The practical implementability of our algorithms will finally be demonstrated by means of simulation and FPGA prototype implementations, which also facilitate some experimental evaluation.

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FATAL

Funding: FWF

Partners: Institut für Elektrische Mess- und Schaltungstechnik (Horst Zimmermann)

Time Frame: 01. 10. 2009 - 31. 03. 2014

Contact Persons: Ulrich Schmid (Project leader), Ao.Univ.Prof. Dr. Andreas Steininger (Co-project leader)

Research Team: Ulrich Schmid (Project leader), Ao.Univ.Prof. Dr. Andreas Steininger (Co-project leader), Matthias Függer (Principal investigator), Jakob Lechner (Principal investigator)

The aim of the FATAL project is the development of the mathematical/formal foundations of a framework for the hierarchical modeling and analysis of fault-tolerant asynchronous VLSI circuits, using fault-tolerant distributed algorithms knowledge in conjunction with the experimental assessment of both radiation-induced failures and metastability in modern VLSI technology. FATAL is a joint project between the Institut für Technische Informatik and the Institut für Elektrische Mess- und Schaltungstechnik at TU Wien.

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PSRTS

Funding: FWF

Time Frame: 26. 02. 2008 - 25. 02. 2011

Contact Persons: Ulrich Schmid (Project head)

Research Team: Ulrich Schmid (Project head), Dipl.-Ing. Heinrich Moser (PhD student), Dipl.-Ing. Peter Robinson (PhD student)

The project "Partially Synchronous Distributed Real-Time Systems" (PSRTS) is devoted to the development of a sound scientific basis for fault-tolerant distributed hard real-time systems with a high degree of concurrency and, hence, relaxed synchrony-by-design. Its purpose is to revise/adapt/extend existing approaches in order to add a proper real-time systems perspective to the theory of distributed algorithms.

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DARTS - Distributed Algorithms for Robust Tick Synchronization

DARTS - Distributed Algorithms for Robust Tick Synchronization

Funding: BMVIT, FIT-IT, FFG, EUTEMA

Partners: Austrian Aerospace GmbH

Time Frame: 01. 10. 2005 - 30. 09. 2008

Contact Persons: Ao.Univ.Prof. Dr. Andreas Steininger (Project Management, Concept Development), Dipl.-Ing. Gottfried Fuchs (Hardware Implementation, Project Management, Evaluation)

Research Team: Ulrich Schmid (Project Head, Algorithm Design & Proofs), Ao.Univ.Prof. Dr. Andreas Steininger (Project Management, Concept Development), Dipl.-Ing. Gottfried Fuchs (Hardware Implementation, Project Management, Evaluation), Dipl.-Ing. Thomas Handl (Testing and Formal Verifcation)

The FIT-IT project DARTS — Distributed Algorithms for Robust Tick Synchronization is dedicated to the development of a novel method to provide synchronous systems with a robust and fault-tolerant clocking methodology to overcome the problems and limitations of currently used approaches.

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ExTract

ExTract

Funding: BMVIT, FIT-IT Embedded Systems, FFG, Eutema

Time Frame: 01. 10. 2005 - 30. 09. 2008

Contact Persons: Ao.Univ.Prof. Dr. Andreas Steininger

Research Team: Ao.Univ.Prof. Dr. Andreas Steininger, Dipl.-Ing. Eric Armengaud

The FIT-IT project ExTraCT — Exploiting Synchrony for Transparent Communication Services Testing — is dedicated to the concept and development of a novel method to enable the transparent testing of time-triggered communication protocols.

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SPAWN

Funding: FWF

Time Frame: 01. 09. 2005 - 31. 08. 2008

Contact Persons: Univ.Ass. Dr. Bettina Weiss

Research Team: Univ.Ass. Dr. Bettina Weiss, Dipl.-Ing. Günther Gridling (research assistant)

The project SPAWN shall develop and analyze failure models, protocols and algorithms for basic fault-tolerant distributed computing problems like consensus and clock synchronization that run directly atop of sparse networks.

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SCDL - Seamless Campus: Distance Labs

Funding: BMVIT, FIT-IT Embedded Systems, FFG, Eutema

Time Frame: 01. 08. 2004 - 31. 01. 2007

Contact Persons: Dipl.-Ing. MMag. Markus Proske

Research Team: Dipl.-Ing. MMag. Markus Proske, Dipl.-Ing. Christian Trödhandl, Dipl.-Ing. Thomas Handl, Dipl.-Ing. Günther Gridling

The Seamless Campus: Distance Labs project (SCDL) is devoted to introduce distance labs in our main hardware-centric courses. The project focuses on two concepts: remote-controlled hardware and carry-out equipment. Another major part of the project is the setup of a surrounding environment to efficiently hold courses in distance education.

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