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Peter Tummeltshammer

 

About:

Peter Tummeltshammer received his Master degree (Diplomingenieur) in Computer Science 2004 from the Vienna University of Technology.  Since September 2004 he was a research assistant at the Institute of Computer Engineering where he was also working on his PhD thesis.

He finished his PhD in 2009 and started working at Thales Austria in the area of railway safety.

His research interests are ASIC and FPGA-design, DSP and fault-tolerant real-time systems.


Projects:

Multiplexed Multiple Constant Multiplication
This project was started during an internship at the Carnegie Mellon University in Pittsburgh, where he worked on the SPIRAL project. The research included multiplierless constant multiplication and automated hardware generation.

Quick Recovery in Dual Core Architectures
This project dealt with quick CPU recovery in the automotive area with a focus on the dual core architecture. The research included prototyping on an FPGA and resulted in several patents with Bosch Germany on recovery mechanisms in dual core architecture.

Analysis of Common Cause Faults in Dual Core Architectures
This project analyzed the probability and effect of common cause faults in dual core architectures. The research included two different fault injection campaigns, one of which was conducted on an industrial ASIC prototoype dual core architecture, and was the cornerstone for the resulting PhD thesis.


Publications:

Multiple Constant Multiplication by Time-Multiplexed Mapping of Addition Chains
Peter Tummeltshammer.
Master's Thesis, 2004. Vienna University of Technology, Embedded Computing Systems Group, Apr. 2004

Multiple Constant Multiplication By Time-Multiplexed Mapping of Addition Chains
Peter Tummeltshammer, James C. Hoe and Markus Püschel.
Proceedings of the 41st Design Automation Conference, DAC'04.
Jul. 2004 Page(s):826 - 829

Recovery Mechanisms for Dual Core Architectures
Christian El Salloum, Andreas Steininger and Peter Tummeltshammer.
21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2006, Oct. 2006.

Time-multiplexed multiple constant multiplication.
Peter Tummeltshammer and Andreas Steininger.
Proceedings of the Junior Scientist Conference, Apr. 2006.

Exploring hardware software partitioning on the example of a face recognition system.
Christoph Angerer, Ondrej Cevan, Loris Fauster, Andreas Fellnhofer, Yilin Huang, Benedikt Huber, Philipp Jahn, Voin Legourski, Simon Pirker, Thomas Polzer, Daniel Reichhard, David Rigler, Alexandra Schuster, Bernhard Weinrich, Martin Delvai and Peter Tummeltshammer.
Austrochip 2007 - Proceedings of the 15th Austrian Workshop on Microelectronics, Graz, Oct. 2007.

Multiplexed Multiple Constant Multiplication
Peter Tummeltshammer, James C. Hoe and Markus Püschel.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(9):1551-1563, 2007.

Exploring hardware software partitioning on the example of a fingerprint verification system.
Stefan Hepp, Georg Klima, Albrecht Kadlec, Lukas Krammer, Werner Luckner, Daniel Prokesch, Stefan Resch, Stefan Tauner, Armin Wasicek, Jakob Wilhelm, Martin Walter, Martin Delvai and Peter Tummeltshammer.
Austrochip 2008 - Proceedings of the 16th Austrian Workshop on Microelectronics, Linz, Oct. 2008.

On the role of the power supply as an entry for common cause faults - an experimental analysis.
Peter Tummeltshammer and Andreas Steininger.
11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS'09, Apr. 2009.

Power supply induced common cause faults - experimental assessment of potential countermeasures.
Peter Tummeltshammer and Andreas Steininger.
IEEE International Conference on Dependable Systems and Networks DSN'09, Jun. 2009.

On the risk of fault coupling over the chip substrate.
Peter Tummeltshammer and Andreas Steininger.
12th Euromicro Conference on Digital System Design, DSD'09, Aug. 2009.

Analysis of Common Cause Faults in Dual Core Architectures
Peter Tummeltshammer.
PhD Thesis, 2009. Vienna University of Technology, Embedded Computing Systems Group